1. Field of the Invention
The present invention relates to a high-voltage switch with low output ripple for non-volatile floating-gate memories, in particular for flash memories.
2. Description of the Related Art
As is known, flash memories are currently used in a vast number of electronic apparatuses, such as for example digital cameras, cell phones, and PDAs, for non-volatile data storage. In particular, flash memories offer the advantage of combining a high programming speed with a high storage density.
According to the organization of the memory cells, flash memories are divided into NOR type and NAND type. As is known, NOR-type memories operate at higher speeds, whilst NAND-type memories have lower speeds but a higher data-storage density.
In synthesis, flash memories comprise an array of memory cells organized in rows (wordlines) and columns (bitlines), each of which is formed by a floating-gate transistor. To execute the operations of reading and modifying (erasing or programming) of the memory cells, it is necessary to send high voltages to the terminals of the individual memory cells (by the term “high voltages” reference is made herein to voltages of a value higher than the supply voltage of the memory). For example, in the case of NAND-type flash memories, in order to execute programming of a memory cell it is necessary to send a programming voltage of approximately 20 V to the control gate terminal.
Generally, high voltages are generated via charge-pump circuits, and transmitted to the memory cells via high-voltage switches comprising NMOS or PMOS pass transistor of a high-voltage type. In a known way, if an appropriate control voltage is applied to the gate terminal of each pass transistor, the high-voltage on a first conduction terminal is transmitted to a second conduction terminal, connected to a respective memory cell.
When it is necessary to boost the voltage of the gate terminal of the pass transistor to a value higher than the high voltage received on the first conduction terminal for ensuring complete transfer of the high voltage at output, the high-voltage switches further comprise a voltage-multiplying circuit connected to the gate terminal of the pass transistor. Said condition arises in all cases where the manufacturing technology does not envisage high-voltage P-channel transistors, or else in the case where high-voltage P-channel transistors are available, but a high negative voltage must be transferred at output.
An example of a high-voltage switch is described in U.S. Pat. No. 6,549,461. This circuit is illustrated in FIG. 1, in which it is designated as a whole by reference number 1.
In detail, the high-voltage switch 1 has a first input terminal IN1, receiving a low supply voltage VDD of, for example, 3 V or less; a second input terminal IN2, receiving a periodic square-wave clock signal CK; a third input terminal IN3, receiving a high voltage HV, having for example a value of 20 V; a fourth input terminal IN4, receiving an enabling signal EN of a logic type, which can assume a first voltage value of 0 V, and a second voltage value, equal to VDD; and an output terminal OUT supplying an output signal Vout.
The high-voltage switch 1 comprises a first NMOS transistor 2, a second NMOS transistor 3, and a third NMOS transistor 4, and a first capacitor 5 and a second capacitor 6. The first NMOS transistor 2 is connected between the fourth input terminal IN4 and an internal node 7, and has a gate terminal connected to the first input terminal IN1. The first capacitor 5 has a first terminal connected to the internal node 7, and a second terminal connected to the second input terminal IN2 via interposition of a first logic inverter 8, and consequently receiving the negated clock signal CK. The second capacitor 6 has a first terminal connected to the second input terminal IN2, and a second terminal connected to the internal node 7, via interposition of the second NMOS transistor 3. The second NMOS transistor 3 is diode-connected, and has its gate terminal connected to the third input terminal IN3 via interposition of the third NMOS transistor 4, which in turn has its gate terminal connected to the internal node 7.
The high-voltage switch 1 further comprises a pass transistor 9 of an NMOS type, and a fourth NMOS transistor 10. The pass transistor 9 has its gate terminal connected to the internal node 7, its first conduction terminal connected to the third input terminal IN3, and its second conduction terminal connected to the output terminal OUT. The fourth NMOS transistor 10 is connected between the output terminal OUT and a reference-voltage node GND, and has its gate terminal connected to the fourth input terminal IN4 through a second logic inverter 11.
On the basis of the value of the enabling signal EN, the high-voltage switch 1 enables or not the transfer of the high voltage HV received at input to the output terminal OUT. Thus, operation of the high-voltage switch 1 envisages two operating states, i.e., a “off” operating state, for example with the enabling signal EN having the first value, when the high voltage HV is not transferred at output (Vout has an approximately zero value), and a “on” operating state, in the example with the enabling signal EN having the second value, when the high voltage HV is transferred at output (Vout has a value approximately equal to HV).
In synthesis, when the enabling signal EN is 0 V, the fourth NMOS transistor 10 conducts and brings the output terminal OUT to the reference voltage GND, so that the output signal Vout assumes an approximately zero value (“off” operating state of the high-voltage switch 1). When, instead, the enabling signal EN has a value of VDD, the first NMOS transistor 2 conducts, and the internal node 7 reaches a voltage of VDD−Vth, where Vth is the threshold voltage of the first NMOS transistor 2. Then, by application of the clock signal CK to the terminals of the first and second capacitors 5, 6, a charge-pump mechanism is triggered, so that the voltage of the internal node 7 is increased by a value equal to VDD at each cycle of the clock signal CK, until it reaches a boosted value of HV+VDD. Said boosted voltage, applied to the gate terminal of the pass transistor 9 enables complete transfer of the high voltage HV to the output terminal OUT, so that the output signal Vout assumes a value approximately equal to HV (“on” operating state of the high-voltage switch 1).
FIG. 2 shows the plot of the output signal Vout and of the voltage of the internal node 7, designated by V7, as a function of time (the initial time corresponding to switching of the enabling signal EN from the first value to the second value); as may be noted, the output signal Vout has a high ripple, which is entirely due to switching of the clock signal CK, in the hypothesis that the high voltage HV is without any ripple. In fact, the gate terminal of the pass transistor 9 is directly connected to the first capacitor 5, and consequently the output signal Vout is directly affected by the voltage fluctuations across the first capacitor 5 due to switching of the clock signal CK. FIG. 3 shows an enlarged portion of the plot of the output signal Vout, in a time interval wherein it has already reached the desired high-voltage value. As may be noted, the ripple has an amplitude of approximately 600 mVpp.
Such a high ripple proves disadvantageous in all the operating steps of the memory, in particular when the memory is of a multilevel type. In this case, in fact, the ripple leads to a widening of the programmed distributions of the threshold voltages of the memory cells, with a consequent decrease in the noise margin during reading. In the worst case, an excessive widening of the distributions may even lead to read failures.